1. Field of the Invention
The present invention relates to a read only memory (ROM), and in particular to improvements in the circuitry and methodology of the subcircuits included within a very large scale integrated (VLSI) ROM.
2. Description of the Prior Art
As shown in FIG. 1, the overall structure of a prior art ROM is typically comprised of an input buffer circuit, an address transition detector circuit (ATD), an X and Y decoder circuit, a sense amplifier for reading the memory cells. A plurality of memory cells are coupled to the input buffer and accessed through the X and Y decoder with their output coupled to the sense amplifier, and to an output buffer circuit having its input coupled to the output of the sense amplifier. The function of the input buffer is to convert a TTL level signal into a voltage level compatible with the ROM when an address signal is received at the ATD circuit. The function of the address transition detector circuit is to detect address transitions from the output of the input buffer in order to generate appropriate timing signals within the ROM. The X and Y decoders decode an address to select a predetermined memory cell within the array. The sense amplifier reads the data stored in the memory cell. The output from the seine amplifier is then buffered to the output circuit for a TTL level output. Such prior an architectures are prone to several limitations as discussed below.
Prior art input buffer circuits typically have an input inverter stage with a threshold of 1.4 volts and operate within a 0.8 low logic level and 2.0 volt high logic level from a 5-volt supply voltage. The output voltage levels of the typical input buffer has a high logic level of 2.4 volts and a low logic level of 0.4 volts. Noise in the power supply line or signal line into the input buffer can often cause a malfunction, particularly at high data rates in an LSI chip. The voltage margins between ground level and the level of the low logic output or between the low level output voltage in the low logic level input voltage is only 0.4 volts.
Therefore, the prior art has attempted to devise a solution wherein the initial input stage inverter of the input buffer is provided with a hysteresis property to prevent an instability which arises from ringing. The ringing can be caused when the input signal is convened from a high to low level or there is a drift or variation in the ground level. FIG. 16 shows a typical prior art circuit having just such a hysteresis property as described in IEEE International Solid State Circuits Conference Digest of Technical Papers (1988), at pages 182-183. The prior art circuit is comprised of two CMOS inverter stages 10 and 12. The output of the first inverter stage 10 is connected to the input of the second inverter stage 12. The output of the second inverter stage 12 is fedback to the gate of a PMOS transistor 14 coupled to the voltage supply VCC. PMOS transistor 14 is turned on when the input is at a low level, thereby maintaining the output of the inverter combination 10 and 12 at a low logic level. The buffer circuit of FIG. 16 can thus not again go high until a voltage of sufficient level and stability is provided to switch both inverter circuits 10 and 12 to turn off load transistor 14 allowing a high logic output.
However, the prior art circuit of FIG. 16 is subject to noise-induced malfunction. The LSI chip itself may create noise when the output buffer circuit is switched, in addition to being subject to externally created noise. The output buffer creates noise when the charge on a load capacitance flows into the ground line of the LSI chip from a driving transistor in the output buffer. A large tramconductance, g.sub.m, of the driving transistor in the output buffer circuit causes the threshold value of an input inverter in the output buffer circuit to be substantially reduced and therefore easily influenced by a noise. For example, in the circuit of FIG. 16, the threshold value of the initial input inverter 10 is inevitably shifted by the high tramconductance of the driving transistor to cancel out the hysteresis property normally provided by load transistor 14 as described above. Hence, the input buffer of FIG. 16 becomes susceptible to noise based malfunctions, either from spikes on the LSI ground line or from externally created noise sources. Furthermore, the input buffer of FIG. 16 has the disadvantage that it cannot be implemented using only an NMOS methodology since PMOS load transistors are required.
Another limitation in the prior art pertains to address transition detection circuits. Conventional address transition detection circuits generate internal timing signals on the occurrence of an address transition. Typically in such an event all internal decode signals are set at a low level for a predetermined period after the address transition. This method is used in order to prevent power consumption caused by invalid addresses which occur during the transient state. However, this methodology results in a change in status of the internal decoding lines twice every time an address transition takes place. For example, after an address becomes valid the internal decoding is changed a first time to reflect the valid address and then goes to an all-logic low state and then transitions a second time to the next valid address. Power consumption is therefore increased at high data rates.
The prior an memories have also experienced shortcomings with respect to the memory array itself. A typical prior an planar memory cell array uses bit lines formed by diffusion layers and word lines of polycide which intersect the bit lines. The source and drain regions of the MOS transistors are defined in the intersections between the word and bit lines. Channels are formed between the source and drain regions. The prior art has employed the concept of utilizing a bank selection methodology to preselect a prescribed memory cell in such a planar memory array. As previously stated, the bit lines are fabricated as diffusion lines and are characterized by approximate 30 ohms per square sheet resistance. Since the pitch of the diffusion lines in the array is about equal to the pitch of the gate wiring, about two diffusion wire sheets are provided for every memory cell providing the source and drain connection for that cell. In the embodiment shown in FIG. 17 there is a resistance of about 2 kilo-ohms for 32 cells in terms of parasitic wiring resistance. This resistance varies from 0 to 2K ohms depending upon the cell's position.
When a memory cell is on, it has an internal resistance of about 19 kilo-ohms assuming that the on-state current is approximately 150 microamps and the bit line voltage is 1.5 volts. As a result, the number of memory cells provided between each group of bank select transistors 20 and 26, for example, is necessarily restricted in order to avoid unacceptable low relative voltage drops across the memory cells. This restriction in the number of cells between the bank select transistors not only decreases the degree of integration which can be achieved on the chip, but also limits the operational speed of the memory array.
As discussed above, the bit lines of such arrays are conventionally made of N+doped diffusion layers while the word lines are constructed of polycide. The selection transistor placed on the even bit lines is, as described, positioned at the upper end of each bit line. The gates of the selection transistors are driven by a common gate selection signal, SE. Similarly, transistors are placed in the lower end of the array for selecting the odd lines and are driven through their gates through a common select signal, SO. The main bit line, typically composed of aluminum, is connected to a contact opposite the nth and nth+1 bit lines. The same main bit line is connected to a contact opposite the nth+1 and nth+2 selection transistor bit lines. Analogously a virtual ground line is connected to the nth+2 and nth+3 odd selection bit transistors as well as the nth+3 and nth+4 even selection transistors. Main bit line 16 is connected directly to bit lines 22a and 22b respectively in the lower portion of the memory array in the proximity of column select transistors 26 and is connected to bit lines 22b and 22c respectively in the upper portion of the array in the vicinity of column select transistors 20. Similarly, the virtual ground line 18 is connected to bit lines 22c and 22d respectively in the lower portion of the array and is directly connected to bit lines (not shown) in the upper portion of the array.
When the even columns of the array are selected, the signal transmission path in the prior art circuit of FIG. 17 includes a path through the corresponding bit line selection transistor 20a, a first bit line, 22c, for example, then back up the target memory transistor 21, through a second bit line, 22d, for example, and then through a corresponding selection transistor 26b to the virtual ground 18. The capacity and resistance of the transmission path of the signal is thus twice that of the length of the bit line within the block. The same is true if the lowest row within an odd column is selected. As a result, such prior memories are subject to speed limitations and a restriction on the number of transistors which can be placed in a row within a single block. The degree of LSI integration is therefore limited.
It can also be readily appreciated by viewing FIG. 17 that the bank select transistors 20 and 26 which are associated with main bit line 16 and virtual ground line 18 are both disposed in the same proximity within the chip. Therefore, any memory cell in the array has a symmetrical wiring resistance in its source and drain wiring relative to main bit line 16 and virtual ground line 18, however, it varies from zero to a large value.
Prior art ROM circuitry also suffered from a limitation in the dynamic timing and control of the output signal. Information is stored in the ROM, depending on whether or not a preset electrical charge is discharged in response to an address signal. This charge is read by a sense circuit. The read decision of a memory cell is made depending on whether a precharge level in the memory cell is changed to a circuit threshold value by a transistor in the memory array. In such a read methodology the difference between the memory cell current and leakage current sometimes cannot be distinguished by the sense amplifier. This causes a malfunction upon generation of unacceptably high leakage currents.
In conventional read-only memories, especially NOR-type memories, fast response times and low power consumption has been difficult to achieve due to poor manipulation of the bit lines. More recently larger and faster memory devices are being developed for NOR-type read-only memories. Thus far, none has utilized any technology which has improved the management of the bit lines within the memory.
A large capacity ROM necessarily contemplates LSI architecture for the memory cells, whether NOR or NAND type. In order to make a conventional large scale and a greater memory cell respond faster, dynamic manipulation of the bit lines has been attempted. However, this approach has resulted in unacceptable power consumption and therefore has not been utilized.
What is needed then is a way to manipulate bit lines in an LSI memory cell dynamically without consuming a large amount of power.
To solve this, one prior art system as described in the 1988 IEEE International Solid State Circuits Conference Digest of Technical Papers, pages 124-125 is provided with reference cells and array cells to detect the difference in current between the array cell and reference cell between the on and off states by adding an offset current only on the on-state reading cycle of the array. While this approach solved the problem of leakage currents, an access delay is caused if the offset current is not equal to the average current flowing through the array cell during both the on and off states. Moreover, it is difficult to generate such an offset current independently of the voltage supply level.
Prior art output buffer circuits have experienced slow switching speeds in the NMOS output transistors. For example, as described in the IEEE Journal of Solid State Circuits, Vol. 23, No. 5, 1988 at pages 1054 1058, an output buffer circuit suppresses the peak of current flowing from an output pin by temporarily setting its output at an intermediate potential between the high and low logic levels. However, since the output is temporarily set at an intermediate potential, current flows through the output circuitry if a CMOS device is provided as the input of the next stage. In the circuit described in the 1988 IEEE Solid State Circuits Conference Digest of Technical Papers, pages 120-121, a bias signal is applied to an NMOS transistor in the final inverter stage of the output buffer circuit through a coupling transistor. The bias voltage is applied to a coupling transistor. Since the bias voltage is fixed between zero volts and the supply voltage, the switching speed of the final stage, NMOS transistor is increased. The increase in switching speed is utilized to suppress the peak current which flows from the output pin to ground when the output level switches from a high to a low logic level. However, since the switching rate of the NMOS transistor is increased, excessive time is required to convert the output to a high output level.
Among the efforts currently being made in the art to produce larger and denser semiconductor devices, is the use of dynamic circuits for constructing larger scale and faster memories. However, a conventional dynamic circuit has a data hold period in the buffer, that is, the period during which data must be held regardless of the circuit's gated diffusion capacity. Therefore, due to pattern layout architecture, performance during hold periods may be erratic. If the signal is affected by coupling noise input through a gate, the transistor may enter a half-on state, if not malfunctioning altogether, because the gate voltage is floating and not driven. This in turn leads to the emission of hot electrons. Hot electrons can affect the reliability of the array and can be substantial where the circuit is highly miniaturized. Therefore, what is needed is a dynamic circuit which is not affected by these coupling noises.
Refer briefly to FIG. 25 which shows a prior art circuit used to deal with noise in an output buffer. Noise is reduced by applying an intermediate voltage or bias to the gate of a transistor 350 when the input signal, IN, changes from the logic low to the logic high to cause transistor 352 to enter a half-on state which would gradually drain the current from the output port to ground. This increases the buffer's time delay when the process variations, device temperatures and/or voltage levels are in their slowest state.
The usual methods to generate a bias level is to generate an analog voltage that varies with temperature and process conditions and that allows some compensation in response to those conditions. In using these prior methods it is difficult to adjust the voltage level. The solution suffers from the limitation and the compensation tends to slow down to the slowest circuit part, thereby causing a substantial degradation in the worse case speed specification in the circuit. It is also important to note that when the circuit is in its slowest condition, compensation may not be necessary and may in effect be detrimental.
In this case, ff the bias voltage is fixed at an intermediate level, delay of the output buffer becomes excessively large even though the noise in the output buffer is reduced. What is needed then is a means and method of solving the problem with a bias voltage supply circuit which can adjust the bias voltage, taking process variations into consideration as well as circuit speed reaction to voltage level.
Therefore, it is an object of this invention to provide a ROM circuit which overcomes each of the above-discussed shortcomings of the prior art. For example, one object of the invention is to avoid noise induced malfunctions caused by the driving transistor in the input buffer circuit.
Another object is to provide an input buffer circuit which is usable in LSI chips based both on NMOS and CMOS technologies.
It is another object of the invention to provide a memory array which can be laid out in a smaller area as well as providing an increase in memory speed or decrease in access time.
It is further an object of the invention to provide a sense circuit in the ROM which can compensate for off-state current of the memory cells and leakage current in the memory cells to avoid malfunction.
It is still further an object of the invention to provide a sense circuit which can adjust loads in response to the driving signal from the memory cells in order to prevent loss of circuit speed and to reduce noise even if the on-state current in the memory cell is varied.
It is still further an object of the invention to provide an output buffer circuit which is not characterized by a high switching current and still has a fast switching speed.